1. Field of the Invention
The disclosure generally relates to a delay locked loop (DLL) circuit, and more particularly, relates to a delay locked loop circuit for improving jitters.
2. Description of the Related Art
With the development of the semiconductor process, very large scale integration (VLSI) system-on-chip (SoC) has become more popular. When systems are integrated on a chip, synchronized clocks are essential elements. Delay locked loop (DLL) circuits or phase locked loop (PLL) circuits are common used to clock/signal phase alignment.
If a real output clock differs from an ideal output clock, a jitter could occur. Jitters are serious problems of DLL or PLL circuits. Traditionally, a master-slave DLL circuit with delay lines of a slave circuit will consume no current without input signals (i.e., input signals are constantly equal to logic level 0 or logic level 1). This leads to a different control voltage between a master circuit and a slave circuit, and leads to jitters.